1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of sophisticated integrated circuits including transistor structures with complex dopant profiles generated on the basis of ion implantation.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to increase the number of transistor elements in order to enhance performance of modern CPUs and the like with respect to operating speed and functionality. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, which may also be referred to as a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. For example, so-called short channel effects may occur for highly scaled transistor elements, resulting in a reduced controllability of the channel region, which may result in increased leakage currents and generally in degraded transistor performance. One challenging task in this respect is, therefore, the provision of appropriately designed junction regions in the form of shallow junctions, at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a moderately high conductivity so as to maintain the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions at a relatively low level, while also controlling the parasitic drain/source capacitance and the electric field of the cut-off region. The requirement for shallow junctions having a relatively high conductivity while providing adequate channel control is commonly met by performing an ion implantation sequence on the basis of a spacer structure so as to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and, therefore, one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability, in turn, is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile. This effect may be advantageous in some cases for defining critical transistor properties, such as the overlap between the extension regions and the gate electrode. On the other hand, the dopant diffusion may also result in a migration of dopants from the shallow extension regions into a portion of the spacer structure, such as a silicon dioxide etch stop or liner material, thereby contributing to a loss of dopants, which may not be readily taken into consideration due to the above-specified limitations. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, since the overall series resistance of the conductive path between the drain and source contacts, as well as the controllability of the channel region, may represent a dominant aspect for determining the transistor performance.
The dopant profiles are adjusted on the basis of a sidewall spacer structure which typically includes one or more spacer elements formed of silicon nitride material in combination with an appropriate etch stop liner material, such as undoped silicon dioxide. Consequently, the width of the spacer structure and thus the definition of the entry point of an implantation species during the complex implantation sequence may be defined on the basis of the initial layer thickness of the spacer layer stack and the corresponding etch process parameters. The patterning of the spacer layer stack is typically accomplished on the basis of sophisticated plasma assisted etch techniques. As is well known, one issue in shrinking overall dimensions of feature sizes is the requirement for patterning the features on the basis of advanced lithography techniques in combination with complex etch processes. In the case of patterning a spacer element, the previously obtained device topography may be advantageously used in order to form the spacer elements in a self-aligned manner on the basis of plasma assisted dry etch techniques, in which a plasma ambient is established by using reactive gas components. The particles in the reactive ambient react with the surface to be etched, wherein, typically, the ambient may cause a different removal rate for different materials that are in contact with the reactive plasma ambient. Moreover, during a plasma assisted etch process, the ions may be accelerated towards the surface to be etched, thereby also imparting a physical component to the removal rate, which contributes to superior directionality of the removal process. In addition, appropriate polymer substances may be added, which may also allow an adjustment of the directionality of the etch front, thereby enabling a highly “anisotropic” etch behavior. The mechanism of plasma etching depends on the capability of the reactive component to form a volatile etch byproduct, which is released into the process ambient, thereby increasingly removing material from the exposed surface. Frequently, it is important to protect deeper lying materials from exposure to the plasma ambient or a defined depth for stopping the etch process across the entire surface is required, which is typically accomplished by providing an etch stop material, which is to be understood as a material having a significantly reduced removal rate compared to the material that is actually to be etched in the plasma ambient. Consequently, the material of interest may be etched “selectively” with respect to the etch stop material, which may be accomplished on the basis of a plurality of well-established etch chemistries. For example, the critical process for forming spacer elements is typically performed by using a material system including the silicon dioxide as an etch stop material and the silicon nitride as the actual spacer material, since, for these materials, highly efficient and selective plasma assisted etch recipes are available.
Upon further shrinking transistor dimensions, the corresponding spacer structures also have to be adapted, wherein, however, the thickness of the etch stop material may not be correspondingly scaled down unless undue material erosion of the etch stop material and of any underlying materials may be caused during the further processing of the device. For instance, although presently available etch chemistries exhibit a very high degree of selectivity for the material system silicon dioxide/silicon nitride, nevertheless a pronounced over etch time may typically have to be applied in order to reliably remove the silicon nitride material from certain device areas across the entire substrate. Consequently, in such areas, the remaining etch stop material may have a significantly reduced thickness or may be entirely removed, thereby exposing these device areas, which may result in significant material loss in subsequent process steps. For instance, a significant material loss may occur in isolation structures relative to adjacent active semiconductor regions, thereby contributing a pronounced surface topography, which, in turn, may negatively affect the further processing and thus the finally achieved performance of sophisticated transistor elements.
Moreover, as previously discussed, extremely sophisticated shallow dopant profiles may be required adjacent to the channel region of the field effect transistors, in particular if extremely short channel transistors are considered, so that a high dopant concentration may be required at a reduced penetration depth. Thereafter, one or more sidewall spacers may typically be required for further profiling the lateral dopant concentration in the drain and source areas, which is accomplished on the basis of the well-established silicon dioxide/silicon nitride material system. Due to the restrictions in view of a minimum thickness of the silicon dioxide etch stop material, however, a moderately thick liner may be in direct contact with the drain and source extension regions, which may result in a significant degree of dopant diffusion during any high temperature processes, thereby resulting in a certain degree of “dopant depletion” of the drain and source extension areas.
Since a further increase in etch selectivity, which would allow the selection of a reduced thickness of the silicon dioxide etch stop material, may be difficult to be achieved on the basis of well-established process recipes, a further device scaling may result in increased transistor variability due to a pronounced dopant out-diffusion from the drain and source extension areas. Moreover, the implementation of other performance increasing mechanisms, such as the provision of strain-inducing dielectric materials above basic transistor configurations and/or the provision of an embedded strain-inducing semiconductor alloy in the drain and source areas of transistors, may also be affected by the fact that a significant topography may be generated during the further processing of the sophisticated transistor devices after forming the well-established silicon dioxide/silicon nitride-based spacer structures.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.